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| rev.1.0 S1R72C05*** data sheet
notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit an d, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of economy, trade and industry or other approval from another government agency. all other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ?seiko epson corporation 2007, all rights reserved. scope this document applies to the ?S1R72C05? usb 2.0 device host controller lsi. S1R72C05*** data sheet (rev.1.00) epson i table of contents 1. over view .................................................................................................................... .1 2. features.................................................................................................................... ..2 3. block diagram ..........................................................................................................3 4. funct ions................................................................................................................... .4 4.1 power supply ............................................................................................................... .................4 4.2 boundary scan.............................................................................................................. ................4 4.2.1 instructi ons suppor ted................................................................................................... ...........4 4.2.2 devi ce_cod e.............................................................................................................. ..........5 4.2.3 terminals excluded from boundar y scan .................................................................................5 4.3 r eset ...................................................................................................................... ........................5 4.3.1 hard reset ............................................................................................................... ................5 4.3.2 soft reset............................................................................................................... ..................5 4.4 cl ock ...................................................................................................................... ........................5 4.5 power ma nageme nt ........................................................................................................... ...........6 4.6 cp u-i/f.................................................................................................................... .......................7 4.7 id e-i/f .................................................................................................................... ........................7 4.8 usb de vice i/f ............................................................................................................. .................7 4.8.1 speed mode and transfer type............................................................................................. ...7 4.8.2 res ources ................................................................................................................ ................7 4.8.2.1 en dpoi nt............................................................................................................... ....................................... 7 4.8.2.2 fifo................................................................................................................... ......................................... 7 4.8.3 data flow ................................................................................................................ .................7 4.8.4 usb device port external circuits........................................................................................ ....9 4.9 usb ho st i/f ............................................................................................................... ...................9 4.9.1 speed mode and transfer type............................................................................................. ...9 4.9.2 res ources ................................................................................................................ ................9 4.9.2.1 chann el................................................................................................................ ....................................... 9 4.9.2.2 fifo................................................................................................................... ......................................... 9 4.9.3 data flow ................................................................................................................ .................9 4.9.4 usb host port external circuits .......................................................................................... ... 11 4.10 fi fo...................................................................................................................... ...................... 11 4.10.1 u sb fifo ................................................................................................................ ............. 11 4.10.2 medi a fifo.............................................................................................................. ............. 11 5. terminal layo ut diagrams ................................................................................12 6. terminal functions ..............................................................................................14 7. electrical c haracteris tics .............................................................................17 7.1 absolute m aximum ratings ................................................................................................... ....17 7.2 recommended oper ating condi tions.......................................................................................17 7.3 dc charact eristi cs......................................................................................................... .............18 7.3.1 current consumpt ion ...................................................................................................... .......18 7.3.2 input char acteristics.................................................................................................... ...........20 7.3.3 output c haracteristics ................................................................................................... .........21 7.3.4 terminal capacit ance ..................................................................................................... ........22 7.4 ac charact eristi cs ......................................................................................................... .............22 7.4.1 rese t timing............................................................................................................. ..............22 ii epson S1R72C05*** da ta sheet (rev.1.00) 7.4.2 clo ck timing ............................................................................................................. ..............22 7.4.3 cpu/dma i/f access timing ................................................................................................ ..23 7.4.3.1 specif ications for cvdd = 1.65 v to 3.6 v .............................................................................. .................. 23 7.4.3.2 specif ications when limited to cvdd = 3.0 v to 3. 6 v ................................................................... ......... 24 7.4.4 ide i/ f timing........................................................................................................... ..............25 7.4.4.1 pio read ti ming ........................................................................................................ ............................... 25 7.4.4.2 pio wr ite ti ming ....................................................................................................... ................................ 26 7.4.4.3 dma read ti ming ........................................................................................................ ............................. 27 7.4.4.4 dma wr ite ti ming ....................................................................................................... .............................. 28 7.4.4.5 ultra dm a read ti ming.................................................................................................. ........................... 29 7.4.4.6 ultra dm a write timing................................................................................................. ............................ 31 7.4.5 usb i/f timing ........................................................................................................... ............32 8. connection example s ..........................................................................................33 8.1 cpu i/f conn ection example................................................................................................. ....33 8.2 usb i/f conn ection example................................................................................................. ....34 8.2.1 for qfp15-128 (device pe riphery) ........................................................................................3 4 8.2.2 for qfp15-12 8 (host pe ripher y)........................................................................................... .35 8.2.3 for pfbga8ux121/pfbga 10ux121 (device peripher y) .....................................................36 8.2.4 for pfbga8ux121/pfbga 10ux121 (host peripher y) .........................................................37 9. product codes .......................................................................................................38 10. external dimens ion diag rams........................................................................39 1. overview S1R72C05*** data sheet (rev.1.00) epson 1 1. overview the S1R72C05** is a usb host and device controller lsi that supports usb 2.0 high-speed mode. separate host and device ports are provided to allow use as a usb host or usb device, depending on how control is switched. an ide i/f is also provided, making it ideal for mobile or car-mounted electronic devices with built-in hdds. 2. features 2 epson S1R72C05*** data sheet (rev.1.00) 2. features < 3. block diagram S1R72C05*** data sheet (rev.1.00) epson 3 3. block diagram htm host sie usb fifo ide master controller cpu i/f controller hdd[15:0] dp_a xrd dm_a vbusflg_a xi xo test mux test tdi xreset tdo dma controller xwrh/xbeh xwrl ca[8:1] cd[15:0] xcs xdack1 xdreq1 xint vbusen_a hda[2:0] xhcs[1:0] xhior xhiow hdmarq xhdmack hiordy hintrq xhreset xhdasp xhpdiag channel/endpoint xdack0 xdreq0 device sie dp_b dm_b dtm r1_a osc & pll60 xbel r1_b 60mhz tck trst tms media fifo media vbus_b fig.3.1 overall block diagram 4. functions 4 epson S1R72C05*** data sheet (rev.1.00) 4. functions 4.1 power supply this lsi has three power supply circuits and a common ground. the power supply circuits consist of hvdd (3.3 v) for usb i/o, ide i/o, and test i/o; cvdd (3.3 v to 1.8 v) for cpu i/f i/o; and lvdd (1.8 v) for internal circuits. (see fig.4.1) i o cpu -i/f fifo h_sie htm cpu usb lvdd hvdd cvdd 1.8v to 3.3v 1.8v 3.3v ide -i/f io test io ide d_sie dtm fig.4.1 S1R72C05 power supplies given below are the sequences for turning the power supplies on and off. this lsi will not operate with only some of the power s upplies turned on or off. the following restrictions apply to the sequence for turning the cvdd/hvdd i/o pow er supplies and lvdd internal power supply on or off. there are no restrictions on the sequence for turning the cvdd and hvdd power supplies on or off. ? the lvdd must be turned on before turning on the cvdd and hvdd power supplies. ? the cvdd and hvdd power supplies must be turned off before turning off the lvdd. if adherence to this sequence is not possible for reasons related to power supply circuit characteristics or load, the cvdd or hvdd must be on for no longer than 1 second while the lvdd is off. 4.2 boundary scan boundary scanning (jtag) may be used when the test terminal is set to ?low? (default). boundary scanning consists of a bs r (boundary scan register) conforming to the jtag (ieee 1149.1) specifications, a connecting scan path, and a tap controller. boundary scan connection information may be provided in bsdl format. 4.2.1 instructions supported this lsi has a jtag instruction bit width of 4 bits and supports the following jtag instructions. 4. functions S1R72C05*** data sheet (rev.1.00) epson 5 table 4.1 jtag instruction codes instruction description code sample/preload loads lsi internal status to bsr and sets data. 0010 bypass bypasses the scan path using bsr. 1111 extest physical device connection check. 0000 clamp bypasses the scan path while maintaining output values. 0011 highz sets all outputs to hi-z. 0100 idcode outputs the spec ified device_code. 0001 4.2.2 device_code the device_code corresponding to an idcode instruction is composed of the following elements. table 4.2 device_code version 1 part number 0x0015 manufacturer 0x0be the device_code response for an idcode instruction will therefore be 0001_0000000000010101_ 00010111110_1. 4.2.3 terminals excluded from boundary scan the following terminals do not include boundary scan cells and are therefore excluded from boundary scanning in this lsi: dp_a, dm_a, dp_b, dm_b, r1_a, r1_b, xi, xo, vbus_b, and test. 4.3 reset this lsi includes a hard reset function via the external xreset terminal and soft reset function via register settings. 4.3.1 hard reset start from reset status when power is turned on, then cancel the reset after confirming power on. 4.3.2 soft reset all lsi circuits can be reset via software, or intern al usb analog macros can be reset individually. the chipreset.allreset bit is used to reset all circuits in this lsi, or the d_reset.resetdtm or h_reset.resethtm bits are used to reset the respective device analog macro or host analog macro. however, note that the analog macro should be reset only in the sleep state. 4.4 clock this lsi contains an internal osci llator and feedback resistor (1 m ? ) and supports clock generation using an external resonator. the oscillator frequency can be set to 12 mhz or 24 mhz via the register settings. fig.4.2 shows a typical connection arrangement for an oscillator circuit. cd, cg, and rd in the oscillator circuit must be matched based on the resonator. contact the resonator manufacturer to obtain circuit constants. 4. functions 6 epson S1R72C05*** data sheet (rev.1.00) xi xo cd rd cg fig.4.2 clock gener ation via the internal oscilla tor and external resonator 4.5 power management this lsi includes a power manage ment function that f eatures six power mana gement states: sleep, snooze, active60, act_device, act_host, and act_all. (see fig.4.3) all function blocks are active in the act_all state (although the usb host function and usb device function cannot be used simu ltaneously). in the sleep state, however, only the circuits necessary for restarting from standby mode are active. intermediate power ma nagement states exist between act_all and sleep, depending on the required activation status. act _ all active inactive cpu -i/f fifo h_sie htm ide-i/f act _ host cpu -i/f fifo ide-i/f d_sie dtm h_sie htm d_sie dtm act _ device cpu -i/f fifo h_sie htm ide-i/f d_sie dtm active 60 cpu -i/f fifo h_sie htm ide-i/f d_sie dtm snooze cpu -i/f * fifo h_sie htm ide-i/f d_sie dtm osc osc osc osc osc pll pll pll pll pll sleep cpu -i/f * fifo h_sie htm ide-i/f d_sie dtm osc pll * the cpu-i/ f is only partially active in the sleep and snooze states, allowing access to the asynchronous access register. fig.4.3 power management states 4. functions S1R72C05*** data sheet (rev.1.00) epson 7 4.6 cpu-i/f this lsi is connected to the cpu via a 16-bit interface. endian settings can be set as big endian or little endian in 16-bit steps. for big endian, registers with even addresses can be accessed above the bus (cd[15:8]), while registers with odd addresses can be accessed below the bus (cd[7:0]). for little endian, registers with even addresses can be accessed below the bus (cd[7:0]), while registers with odd addresses can be accessed above the bus (cd[15:8]). the bus mode can be set to either strobe mode for accessing using high/low strobe (xwrh/xwrl) or byte enable mode for accessing using high/low byte enable (xbeh/xbel) for writing in 8-bit. endian and bus mode are set by the cpuif_mode register immediately after resetting. the cpu-i/f on this lsi incl udes 2-ch dma (slave). the registers that are accessible will depend on the powe r management state. for detailed information, refer to the lsi technical manual. 4.7 ide-i/f this lsi includes an ide host function supporting ata/atapi6, which supports pio modes 0 to 4, multi word dma, and udma modes 0 to 5 transfer modes. 4.8 usb device i/f this lsi supports high-speed specification usb device f unctions that comply with usb 2.0 (universal serial bus specification revisi on 2.0) standards. 4.8.1 speed mode and transfer type this lsi supports hs (480 mbps) and fs (12 mbps) speed modes when operating usb devices. the speed mode is automatically set by the speed negotiations perfo rmed when the bus is reset. for example, hs transfer mode will be selected automatically by speed negotiations if connected to a usb host that supports hs speed mode. (note that fs speed mode can be set deliberately via register settings.) all transfer types stipulated in the usb 2.0 standard are supported, including control transfer (endpoint 0), bulk, interrupt, and isochronous transfers. 4.8.2 resources 4.8.2.1 endpoint this lsi includes endpoint 0 and five standard endpoints. endpoint 0 supports control transfer. the standard endpoints support bulk, interrupt, and isochronous transf ers. the standard endpoint numbers, maximum packet size, and transfer direction (in/out) can be set as desired. 4.8.2.2 fifo this lsi includes 4.5 kb of fifo for use with usb data transfer. this forms the data transfer route with usb. the fifo capacity for each endpoint can be assigned as desired through software. for example, performance can be improved by assigning an adequate fifo area to the endpoints for bulk transfers. 4.8.3 data flow endpoints are assigned to usb fifo areas on a one-to-one basis. responses are retu rned to usb transactions automatically, depending on the usb fifo effective free capacity (for out transfer) or effective data quantity (for in transfer). thus, the software need not be directly involved in individual transactions, allowing usb data 4. functions 8 epson S1R72C05*** data sheet (rev.1.00) transfers to be controlled as data flow on the usb fifo. usb fifo endpoint usb host i n t o k e n d a t a q u a n t i t y < m a x p k t s i z e n a k h a n d s h a k e i n t o k e n d a t a q u a n t i t y > = m a x p k t s i z e d a t a p a c k e t ac k h a n d s h a k e cpu w r i t e f i f o _ em p t y f i f o _ em p t y w r i t e i n t o k e n d a t a q u a n t i t y < m a x pk t si z e write read in transaction (nak response) in transaction (data reply) in transaction (nak response) t ra n s f e r s e n t n a k h a n d s h a k e f i f o _ f u l l f i f o _ f u l l i n t o k e n d a t a q u a n t i t y > = m a x p k t s i z e d a t a p a c k e t ac k h a n d s h a k e in transaction (data reply) empty data fig.4.4 typical data flow (with fifo assigned for maxpktsize and in transfer) usb fifo endpoint usb host pi n g t o k e n f r e e q u a n t i t y > = m a x p k t s iz e a c k h a n d s h a k e o u t t o k e n cpu f i f o _ em p t y pi n g t o k e n f re e q u a n t i t y < m a x pk t si z e read write ping transaction (ack response) out transaction (data receipt) ping transaction (nak response) t ra n s f e r re c e i v e d n a k h a n d s h a k e f i f o _ f u l l f i f o _ em p t y pi n g t o k e n f re e q u a n t i t y > = m a x pk t s i z e ping transaction (ack response) empty data d a t a p a c k e t n y et h a n d s h a k e r e a d ac k h a n d s h a k e note: ping transactions are performed only in high speed mode. fig.4.5 typical data flow (with fifo assigned for maxpktsize and out transfer) 4. functions S1R72C05*** data sheet (rev.1.00) epson 9 4.8.4 usb device port external circuits this lsi has internal fs and hs device termination resistors, eliminating the need for additional components normally used to adjust impedance. this allows a dp/dm line to be connected between the lsi terminal and the connector. the appropriate components should be used to protect against static electricity and implement emi precautions. the vbus terminal uses a 5 v input and does not requir e external voltage conversion. however, a protection circuit is recommended since certain commercially available usb host and hub products may apply surge voltages that exceed vbus ratings. refer to the ?pcb design guidelines for s1r72v series usb 2.0 high-speed devices? provided separately. 4.9 usb host i/f this lsi supports high-speed specification usb host functions that comply with usb 2.0 (universal serial bus specification revisi on 2.0) standards. 4.9.1 speed mode and transfer type this lsi supports hs (480 mbps), fs (12 mbps) and ls (1.5 mbps) speed modes when operating usb hosts. the speed mode is automatically set through speed negotiation performed when the bus is reset. all transfer types stipulated in the usb 2.0 standard are supported, including control, bulk, interrupt, and isochronous transfers. 4.9.2 resources 4.9.2.1 channel in this lsi, the setting register sets for transfers wi th end points on a one-to-one basis are referred to as channels. this lsi features one dedicated channel for cont rol transfers, one dedicated channel for bulk transfers, and four general channels that support bulk, interru pt, and isochronous transfers. the endpoint number, maximum packet size, and transfer direction (in/out) can be set as desired for all channels. transfers are also possible for a number of endpoints exceeding the number of channels using time-multiplexing for channels via software. 4.9.2.2 fifo this lsi includes 4.5 kb of fifo for use with usb data transfers. this forms the data transfer route with usb. the fifo capacity for each chan nel can be assigned as desired vi a software. for ex ample, performance can be improved by assigning a sufficient fifo area to the channels for bulk transfers. 4.9.3 data flow the channels are assigned to fifo areas on a one-to-on e basis, and transactions are automatically sent via usb, depending on the fifo effectiv e free capacity (for in transfers) or effective data quantity (for out transfers). the software need not be directly involved in individual transactions, al lowing the usb data transfer to be controlled as data flow on the fifo. 4. functions 10 epson S1R72C05*** data sheet (rev.1.00) fifo cpu channel usb device n a k h a n d s h a k e i n t o k e n f r e e q u a n t i t y > = m a x p k t s i z e f re e q u a n t i t y < m a x p k t s i z e t r a n s f e r re c e i v e d f r e e q u a n t i t y > = m a x p k t s i z e f i f o _ e m p t y read write f i f o _ f u l l f i f o_ e m p t y empty data r e a d d a t a p a c k e t i n t o k e n a c k h a n d s h a k e i n t o k e n n a k h a n d s h a k e in transaction (nak response) in transaction (nak response) in transaction (data reply) fig.4.6 typical data flow (with fifo as signed for maxpktsize and in transfers) fifo channel usb device d a t a q u a n t i t y < m a x p k t s i z e d a t a q u a n t i t y > = m a x p k t s i z e cpu w r i te f i f o _ em p t y f i f o _ em p t y w r i te d a t a q u a n t i t y < m a x p k t s i z e write read t ra n s f e r s e n t f i f o_ f u l l f i f o_ f u l l d a t a q u a n t i t y > = m a x p k t s i z e o u t t o k e n d a t a p a c k e t a c k h a n d s h a k e o u t t o k e n d a t a p a c k e t a c k h a n d s h a k e empty data out transaction out transaction t ra n s f e r s e n t fig.4.7 typical data flow (with fifo as signed for maxpktsize and out transfers) 4. functions S1R72C05*** data sheet (rev.1.00) epson 11 4.9.4 usb host port external circuits this lsi features internal usb host termination resistors, including hs termination resistors, eliminating the need for the external components typically used to adjust impedance. this allows the connection of a dp/dm line between the lsi terminal and the connector. however, note that the appropriate components should be used to protect against static electricity and to implement emi precautions. external vbus control components are required for vbus. 4.10 fifo 4.10.1 usb fifo this lsi includes 4.5 kb of usb fifo for use with usb data transfers. this is shared between usb device i/f and usb host i/f. the usb fifo capacity for each endpoint or channel can be assigned as desired via software. transfers are possible between the usb-i/f and cpu-i/f via the usb fifo or directly between the usb-i/f and ide-i/f. 4.10.2 media fifo this lsi includes 64 b of media fifo for use with ide data transfers. this forms the data transfer route with the ide-i/f and cpu-i/f. data ca nnot be transferred to or fro m the usb-i/f with media fifo. 5. terminal layout diagrams 12 epson S1R72C05*** data sheet (rev.1.00) 5. terminal layout diagrams hintrq xhdmack hiordy xhior xhiow hdmarq hdd15 hvdd hdd0 hdd14 hdd1 vss hdd13 hdd2 hdd12 hdd3 hvdd vss lvdd hdd11 hdd4 hdd10 hdd5 vss hdd9 hdd6 hdd8 hdd7 xhreset vss lvdd hvdd 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 hda1 97 64 cvdd xhpdiag 98 63 lvdd hda0 99 62 cd15 lvdd 100 61 cd14 vss 101 60 cd13 hvdd 102 59 cd12 hda2 103 58 cd11 xhcs0 104 57 cd10 xhcs1 105 56 cd9 xhdasp 106 55 cd8 vbusflg_a 107 54 vss vbusen_a 108 53 cd7 lvdd 109 52 cd6 vss 110 51 cd5 r1_a 111 50 vss vss 112 49 cvdd hvdd 113 48 cd4 dm_a 114 47 cd3 vss 115 46 cd2 dp_a 116 45 cd1 hvdd 117 44 cd0 lvdd 118 43 vss vss 119 42 lvdd test 120 41 xdack1 tdo 121 40 xdreq1 tck 122 39 xdack0 hvdd 123 38 xdreq0 tms 124 37 xint tdi 125 36 vss trst 126 35 cvdd lvdd 127 34 vss xi 128 33 xwrl 123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 xo vss lvdd vss r1_b vss vss hvdd dm_b vss dp_b hvdd vbus_b lvdd vss n.c. lvdd vss cvdd xreset xbel ca1 ca2 ca3 ca4 ca5 ca6 ca7 ca8 xcs xrd xwrh S1R72C05f00axxx q fp15-128 fig.5.1 qfp package terminal layout diagram 5. terminal layout diagrams S1R72C05*** data sheet (rev.1.00) epson 13 1234567891011 nc xi lvdd lvdd dp_a dm_a hvdd r1_a lvdd hda0 nc a xo vss trst vss hvdd vss vbusen_a vss vss hda2 xhpdiag b lvdd vss tdi tck test xhcs0 vbusflg_a vss xhcs1 hda1 hintrq c r1_b vss tdo xhdasp hvdd xhdmack hiordy xhiow xhior hdd0 hdmarq d hvdd tms vss lvdd vss hdd14 hdd15 hdd12 vss hdd2 hdd13 e dm_b vss vss ca2 vss lvdd hdd3 vss hdd1 vss hvdd f dp_b hvdd vbus_b ca3 xint xdack1 hvdd hdd11 hdd5 hdd10 hdd4 g lvdd vss cvdd ca4 xdack0 cd3 cd6 cvdd cd13 hdd8 hdd9 h lvdd xreset ca1 xbel xdreq1 cd0 cd4 cd7 cd10 hdd6 hdd7 j ca8 xcs ca5 ca6 ca7 cd1 cd5 cd9 cd12 cd14 xhreset k nc xrd xwrh xwrl xdreq0 cd2 cvdd cd8 cd11 cd15 nc l 1234567891011 S1R72C05/pfbga8ux121,pfbga10ux121 top view fig.5.2 bga package terminal layout diagram 6. terminal functions 14 epson S1R72C05*** data sheet (rev.1.00) 6. terminal functions osc pin ball name i/o reset terminal type terminal description 128 a2 xi in - analog internal oscillator circuit input (12 mhz, 24 mhz) 1 b1 xo out - analog internal oscillator circuit output test pin ball name i/o reset terminal type terminal description 120 c5 test in - - test terminal (must be fixed at low) 121 d3 tdo out hi-z 2ma boundary scan tdo terminal 122 c4 tck in - - boundary scan tck terminal 124 e2 tms in - - boundary scan tms terminal 125 c3 tdi in - - boundary scan tdi terminal 126 b3 trst in - - boundary scan trst terminal if the boundary scan function is not used, the test, tck, tms, tdi, and trst terminals should all be set to low and the tdo terminal left open. pd: pull down pu: pull up usb pin ball name i/o reset terminal type terminal description 111 a8 r1_a in - analog internal operation reference current setting terminal (connect 6.2 k ? 1% resistance between vss) 116 a5 dp_a bi hi-z analog usb host data line (data +) 114 a6 dm_a bi hi-z analog usb host data line (data -) 107 c7 vbusflg_a in (pu) schmitt (pu) usb power switch fault detection signal (1: normal, 0: error) 108 b7 vbusen_a out lo 2ma usb power switch control signal 5 d1 r1_b in - analog internal operation reference current setting terminal (connect 6.2 k ? 1% resistance between vss) 11 g1 dp_b bi hi-z analog usb device data line (data +) 9 f1 dm_b bi hi-z analog usb device data line (data -) 13 g3 vbus_b in (pd) (pd) usb device bus detection signal pd: pull down pu: pull up 6. terminal functions S1R72C05*** data sheet (rev.1.00) epson 15 cpu i/f pin ball name i/o reset terminal type terminal description bus mode ? 16bit strobe mode 16bit be mode 20 j2 xreset in - - reset signal 31 l2 xrd in - - read strobe 33 l4 xwrl (xwr) in - - write strobe (lower) write strobe 32 l3 xwrh (xbeh) in - - write strobe (upper) high-byte enable 30 k2 xcs in - - chip select signal 37 g5 xint out high 2ma (tri-state) interrupt signal 38 l5 xdreq0 out high 2ma dma0 request 39 h5 xdack0 in - - dma0 acknowledge 40 j5 xdreq1 out high 2ma dma1 request 41 g6 xdack1 in - - dma1 acknowledge 21 j4 xbel in - - must be fixed at high or low low-byte enable 22 j3 ca1 in - - 23 f4 ca2 in - - 24 g4 ca3 in - - 25 h4 ca4 in - - 26 k3 ca5 in - - 27 k4 ca6 in - - 28 k5 ca7 in - - 29 k1 ca8 in - - cpu bus address 44 j6 cd0 bi hi-z 2ma 45 k6 cd1 bi hi-z 2ma 46 l6 cd2 bi hi-z 2ma 47 h6 cd3 bi hi-z 2ma 48 j7 cd4 bi hi-z 2ma 51 k7 cd5 bi hi-z 2ma 52 h7 cd6 bi hi-z 2ma 53 j8 cd7 bi hi-z 2ma 55 l8 cd8 bi hi-z 2ma 56 k8 cd9 bi hi-z 2ma 57 j9 cd10 bi hi-z 2ma 58 l9 cd11 bi hi-z 2ma 59 k9 cd12 bi hi-z 2ma 60 h9 cd13 bi hi-z 2ma 61 k10 cd14 bi hi-z 2ma 62 l10 cd15 bi hi-z 2ma cpu data bus the xint terminal can be set to 1/0 or hi-z/0 mode, depending on register settings. pd: pull down pu: pull up 6. terminal functions 16 epson S1R72C05*** data sheet (rev.1.00) ide i/f pin ball name i/o reset terminal type terminal description 103 b10 hda2 out hi-z 4ma 97 c10 hda1 out hi-z 4ma 99 a10 hda0 out hi-z 4ma ide register address 105 c9 xhcs1 out hi-z 4ma control register access chip select 104 c6 xhcs0 out hi-z 4ma command block register access chip select 93 d9 xhior out hi-z 4ma ide read strobe 92 d8 xhiow out hi-z 4ma ide write strobe 91 d11 hdmarq in (pd) (pd) dma transfer request 95 d6 xhdmack out hi-z 4ma dma transfer acknowledgement 94 d7 hiordy in (pu) (pu) ide register ready signal 96 c11 hintrq in (pd) (pd) ide interrupt request 68 k11 xhreset out hi-z 4ma ide bus reset 106 d4 xhdasp in (pu) (pu) drive enable/slave drive available 98 b11 xhpdiag in (pu) (pu) diagnostic sequence end signal 90 e7 hdd15 bi hi-z 4ma(pu) 87 e6 hdd14 bi hi-z 4ma(pu) 84 e11 hdd13 bi hi-z 4ma(pu) 82 e8 hdd12 bi hi-z 4ma(pu) 77 g8 hdd11 bi hi-z 4ma(pu) 75 g10 hdd10 bi hi-z 4ma(pu) 72 h11 hdd9 bi hi-z 4ma(pu) 70 h10 hdd8 bi hi-z 4ma(pu) 69 j11 hdd7 bi (pd) 4ma(pd) 71 j10 hdd6 bi hi-z 4ma(pu) 74 g9 hdd5 bi hi-z 4ma(pu) 76 g11 hdd4 bi hi-z 4ma(pu) 81 f7 hdd3 bi hi-z 4ma(pu) 83 e10 hdd2 bi hi-z 4ma(pu) 86 f9 hdd1 bi hi-z 4ma(pu) 88 d10 hdd0 bi hi-z 4ma(pu) ide data bus pu and pd can be turned on or off via register settings. pd: pull down pu: pull up note: the ide i/f terminals are all 5-v tolerant. power pin ball name voltage terminal description 8, 12, 65, 80, 89, 102, 113, 117, 123 g7, d5, f11, e1, g2, b5, a7 hvdd 3.3v power supply for ide i/f i/o, usb i/o, and test i/o 19, 35, 49, 64 h3, l7, h8 cvdd 1.8 to 3.3 v power supply for cpu i/f i/o 3, 14, 17, 42, 63, 66, 78, 100, 109, 118, 127 j1, e4, f6, h1, a3, a4 , c1, a9 lvdd 1.8v osc i/o and internal power supply 2, 4, 6, 7, 10, 15, 18, 34, 36, 43, 50, 54, 67, 73, 79, 85, 101, 110, 112, 115, 119 f3, e3, e5, f5, c8, f8, e9, f10, h2, f2, b2, b4, b6, b8, d2, c2, b9 vss 0v gnd 16 a1, l1, a11, l11 n.c. 0v nc terminal (connect to gnd) 7. electrical characteristics S1R72C05*** data sheet (rev.1.00) epson 17 7. electrical characteristics 7.1 absolute maximum ratings item symbol rating units hvdd vss - 0.3 to 4.0 v cvdd vss - 0.3 to 4.0 v power supply voltage lvdd vss - 0.3 to 2.5 v hvi vss - 0.3 to hvdd + 0.5 v cvi * 1 vss - 0.3 to cvdd + 0.5 v ivi * 2 vss - 0.3 to 5.5 v vvi * 3 vss - 0.3 to 6.0 v input voltage lvi * 4 vss - 0.3 to lvdd + 0.5 v hvo vss - 0.3 to hvdd + 0.5 v output voltage cvo * 1 vss - 0.3 to cvdd + 0.5 v output current/terminal iout 10 ma storage temperature tstg -65 to 150 c * 1 cpu-i/f * 2 ide-i/f * 3 vbus_b * 4 xi 7.2 recommended op erating conditions item symbol min. typ. max. units hvdd 3.00 3.30 3.60 v cvdd 1.65 - 3.60 v power supply voltage lvdd 1.65 1.80 1.95 v hvi -0.3 - hvdd+0.3 v cvi * 1 -0.3 - cvdd+0.3 v ivi * 2 -0.3 - 5.5 v vvi * 3 -0.3 - 6.0 v input voltage lvi * 4 -0.3 - lvdd+0.3 v ambient temperature ta -40 25 85 c * 1 cpu-i/f * 2 ide-i/f * 3 vbus_b * 4 xi power to the ic should be turned on in the sequence shown below. lvdd (internal) hvdd, cvdd (io section) likewise, power to the ic should be turned off in the sequence shown below. hvdd, cvdd (io section) lvdd (internal) note: avoid leaving the hvdd or cvdd on continuously (for more than 1 second) when the lvdd is off, since doing so ma y affect the ch ip reliability. 7. electrical characteristics 18 epson S1R72C05*** data sheet (rev.1.00) 7.3 dc characteristics 7.3.1 current consumption item symbol condition min. typ. max. units power supply feed current * 1 power supply current iddh hvdd = 3.3v(typ), hvdd = 3.6v(max) - 41 65 ma iddch cvdd = 3.3v(typ), cvdd = 3.6v(max) - 1 4 ma iddcl cvdd = 1.8v(typ), cvdd = 1.95v(max) - 0.7 2 ma iddl lvdd = 1.8v(typ), lvdd = 1.95v(max) - 75 120 ma stationary current * 2 power supply current idds vin = hvdd,cvdd,lvdd or vss hvdd = 3.6v cvdd = 3.6v lvdd = 1.95v - - 80 a input leakage input leakage current il hvdd = 3.6v cvdd = 3.6v lvdd = 1.95v hvih = hvdd cvih = cvdd lvih = lvdd vil = vss -5 - 5 a input leakage input leakage current (5-v tolerant) ilif hvdd = 3.0v cvdd = 1.65v lvdd = 1.65v hvoh = 5.5v -10 - 10 a * 1: typ values are measured with the usb-hdd connec ted as usb host and when transferring data between the ide-hdd and usb-hdd (actual transfer rate 30 mb/s). max. values are estimated from these values. * 2: stationary current with ta = 25 c and both terminals in input mode. 7. electrical characteristics S1R72C05*** data sheet (rev.1.00) epson 19 current consumption measurements for various power management states using seiko epson operating conditions (ta = 25 c) item condition min. typ. max. units sleep cpu bus operation * 1 * 2 power supply power hvdd = 3.3v cvdd = 3.3v lvdd = 1.8v - 0.23 - mw snooze cpu bus operation * 1 * 2 power supply power hvdd = 3.3v cvdd = 3.3v lvdd = 1.8v - 1.8 - mw active60(ide ? cpu) * 3 power supply power hvdd = 3.3v cvdd = 3.3v lvdd = 1.8v - 41 - mw act_device(ide ? usb) * 4 power supply power hvdd = 3.3v cvdd = 3.3v lvdd = 1.8v - 131 - mw act_host(ide ? usb) copy * 5 power supply power hvdd = 3.3v cvdd = 3.3v lvdd = 1.8v - 134 - mw act_host(ide ? usb) direct copy * 6 power supply power hvdd = 3.3v cvdd = 3.3v lvdd = 1.8v - 273 - mw * 1: when the cpu is accessing memory (e.g., sram or rom) connected to the cpu bus. * 2: excluding current consumption due to intern al S1R72C05 dp pull-up resistor (approx. 200 a). * 3: when transferring data between the ide-hdd and cpu (actual transfer rate 4 mb/s). * 4: when connected to the pc as a usb device and when transferring data between the ide-hdd and usb (actual transfer rate 25 mb/s). * 5: with the usb-hdd connected as usb host and when transferring data between the ide-hdd and usb-hdd (actual transfer rate 5.3 mb/s). * 6: with the usb-hdd connected as usb host and when transferring data between the ide-hdd and usb-hdd (actual transfer rate 30 mb/s). 7. electrical characteristics 20 epson S1R72C05*** data sheet (rev.1.00) 7.3.2 input characteristics item symbol condition min. typ. max. units input characteristics (lvcmos) terminal name: test, tdi, tck, trst, tms h-level input voltage vih1 hvdd = 3.6v 2.2 - - v l-level input voltage vil1 hvdd = 3.0v - - 0.8 v input characteristics (lvcmos) terminal name: ca[8:1], cd[15:0], xcs, xrd, xwrl, xwrh, xbel, xdack0, xdack1, xreset h-level input voltage vih2 cvdd = 3.6v 2.2 - - v l-level input voltage vil2 cvdd = 3.0v - - 0.8 v h-level input voltage vih3 cvdd = 1.95v 1.27 - - v l-level input voltage vil3 cvdd = 1.65v - - 0.57 v input characteristics (lvcmos) terminal name: hdd[15:0], hdmarq, hiordy, hintrq, xhdasp, xhpdiag h-level input voltage vih4 hvdd = 3.6v 2.2 - - v l-level input voltage vil4 hvdd = 3.0v - - 0.8 v schmitt input characteristics terminal name: vbusflg_a h-level trigger voltage vt+ hvdd = 3.6v 1.4 - 2.7 v l-level trigger voltage vt- hvdd = 3.0v 0.6 - 1.8 v hysteresis voltage ? v hvdd = 3.0v 0.3 - - v schmitt input characteristics (usb fs) terminal name: dp_a, dm_a, dp_b, dm_b h-level trigger voltage vt+(usb) hvdd = 3.6v 1.1 - 1.8 v l-level trigger voltage vt-(usb) hvdd = 3.0v 1.0 - 1.5 v hysteresis voltage ? v(usb) hvdd = 3.0v 0.1 - - v input characteristics (usb fs differential) terminal name: dp_a + dm_a pair, dp_b + dm_b pair differential input sensitivity vds(usb) hvdd = 3.0v differential input voltage = 0.8 v to 2.5 v - - 0.2v v input characteristics (vbus) terminal name: vbus_b h-level trigger voltage vt+(vbus) hvdd = 3.6v 1.86 - 2.85 v l-level trigger voltage vt-(vbus) hvdd = 3.0v 1.48 - 2.23 v hysteresis voltage ? v(vbus) hvdd = 3.0v 0.31 - 0.64 v input characteristics terminal name: hdd[15:8], hdd[6:0], hiordy, xhdasp , xhpdiag, vbusflg_a pull-up resistor rplu vil = vss 50 100 240 k ? input characteristics terminal name: hdd[7], hdmarq, hintrq pull-down resistor rpld vih = hvdd 50 100 240 k ? input characteristics terminal name: vbus_b pull-down resistor rpldv vih = 5.0v 110 125 150 k ? 7. electrical characteristics S1R72C05*** data sheet (rev.1.00) epson 21 7.3.3 output characteristics item symbol condition min. typ. max. units output characteristics terminal nam e: cd[15:0], xdreq0, xdreq1, xint h-level output voltage voh1 cvdd = 3.0v ioh = -2ma cvdd- 0.4 - - v l-level output voltage vol1 cvdd = 3.0v iol = 2ma - - vss+0.4 v h-level output voltage voh2 cvdd = 1.65v ioh = -1ma cvdd- 0.4 - - v l-level output voltage vol2 cvdd = 1.65v iol = 1ma - - vss+0.4 v output characteristics terminal name: hdd[15:0], hda[2:0], xhcs1, xhcs0, xhior, xhiow, xhdmack, xhreset h-level output voltage voh3 hvdd = 3.0v ioh = -4ma hvdd- 1.0 - - v l-level output voltage vol3 hvdd = 3.0v iol = 4ma - - vss+0.4 v output characteristics terminal name: tdo, vbusen_a h-level output voltage voh4 hvdd = 3.0v ioh = -2ma hvdd- 0.4 - - v l-level output voltage vol4 hvdd = 3.0v iol = 2ma - - vss+0.4 v output characteristics (usb fs) terminal name: dp_a, dm_a, dp_b, dm_b h-level output voltage voh(usb) hvdd=3.0v 2.8 - - v l-level output voltage vol(usb) hvdd=3.6v - - 0.3 v output characteristics (usb hs) terminal name: dp_a, dm_a, dp_b, dm_b h-level output voltage vhsoh (usb) hvdd = 3.0v 360 - - mv l-level output voltage vhsol (usb) hvdd = 3.6v - - 10.0 mv output characteristics terminal name: cd[15:0], xint off-state leakage current ioz hvdd = 3.6v cvdd = 1.95v cvoh = cvdd vol = vss -5 - 5 a output characteristics terminal name: hdd[15:0], hda[2:0], xhcs1, xhcs0, xhior, xhiow, xhdmack, xhreset off-state leakage current (5-v tolerant) iozhf hvdd = 3.0v hvoh = 5.5v -10 - 10 a 7. electrical characteristics 22 epson S1R72C05*** data sheet (rev.1.00) 7.3.4 terminal capacitance item symbol condition min. typ. max. units terminal capacitance terminal name: all input terminals input terminal capacitance ci f = 10mhz hvdd = cvdd = lvdd = vss - - 10 pf terminal capacitance terminal name: all output terminals output terminal capacitance co f = 10mhz hvdd = cvdd = lvdd = vss - - 10 pf terminal capacitance terminal name: all input/output terminals (except dp_a, dm_a, dp_b, dm_b) input/output terminal capacitance 1 cio1 f = 10mhz hvdd = cvdd = lvdd = vss - - 10 pf terminal capacitance terminal name: dp_a, dm_a, dp_b, dm_b input/output terminal capacitance 2 cio2 f = 10mhz hvdd = cvdd = lvdd = vss - - 10 pf 7.4 ac characteristics 7.4.1 reset timing xreset t reset code description min. typ. max. units t reset reset pulse width 40 - - ns 7.4.2 clock timing xi t cyc t cycl t cych code description min. typ. max. units t cyc clock cycle (clkselect=0) 11.999 12 12.001 mhz t cyc clock cycle (clkselect=1) 23.998 24 24.002 mhz t cych t cycl clock duty 45 - 55 % 7. electrical characteristics S1R72C05*** data sheet (rev.1.00) epson 23 7.4.3 cpu/dma i/f access timing 7.4.3.1 specifications for cvdd = 1.65 v to 3.6 v xdreq0/1(o) xdack0/1(i) xcs(i) xrd(i) cd(o) valid t cas ca(i) xwrh/l(i) xwr cd(i) code t cas t ccs min. 6 6 typ. - - max. - - unit ns ns t cch t cah 6 6 - - - - ns ns t rbd 1 - - ns t rdf - - 35 ns t rdh 3 - - ns t rbh - - 10 ns t wds t wdh - 6 - - 10 - ns ns t drn - - 35 ns t daa t dan 6 6 - - - - ns ns t cah t ccs t cch t rbd t rdf t rdh t rbh t wds t wdh t drn t daa t dan write read t ras t ras 40 - - ns t was 40 - - ns t was t rng t wng t wcy t rcy t rcy 80 - - ns t rng 25 - - ns 80 - - ns t wcy 25 - - ns t wng xbeh/l(i) t wbs t wbh t wbs t wbh 6 6 - - - - ns ns write byte enable hold time (cl=30pf) item address setup time address hold time xcs setup time xcs hold time read data output start time read data confirmation time read data hold time read data output delay time write data acknowledge delay time write data hold time (after strobe negation) xdreq0/1 negate delay time xdack0/1 setup time xdack0/1 hold time read strobe assert time write strobe assert time read cycle read strobe negate time write cycle write strobe negate time write byte enable setup time t wah 50 - - ns write data hold time (after strobe assertion) t wah t ccn t ccn 15 - - ns xcs negate time (only when cpuif mode is set * ) * for details of cpuif mode setting, refer to ?technical manual.? 7. electrical characteristics 24 epson S1R72C05*** data sheet (rev.1.00) 7.4.3.2 specifications when limited to cvdd = 3.0 v to 3.6 v xdreq0/1(o) xdack0/1(i) xcs(i) xrd(i) cd(o) valid t cas ca(i) xwrh/l(i) xwr cd(i) code t cas t ccs min. 6 6 typ. - - max. - - unit ns ns t cch t cah 6 6 - - - - ns ns t rbd 1 - - ns t rdf - - 30 ns t rdh 3 - - ns t rbh - - 10 ns t wds t wdh - 6 - - 10 - ns ns t drn - - 30 ns t daa t dan 6 6 - - - - ns ns t cah t ccs t cch t rbd t rdf t rdh t rbh t wds t wdh t drn t daa t dan write read t ras t ras 37 - - ns t was 37 - - ns t was t rng t wng t wcy t rcy t rcy 75 - - ns t rng 25 - - ns 75 - - ns t wcy 25 - - ns t wng xbeh/l(i) t wbs t wbh t wbs t wbh 6 6 - - - - ns ns write byte enable hold time (cl=30pf) item address setup time address hold time xcs setup time xcs hold time read data output start time read data confirmation time read data hold time read data output delay time write data acknowledge delay time write data hold time (after strobe negation) xdreq0/1 negate delay time xdack0/1 setup time xdack0/1 hold time read strobe assert time write strobe assert time read cycle read strobe negate time write cycle write strobe negate time write byte enable setup time t wah 50 - - ns write data hold time (after strobe assertion) t wah t ccn 15 - - ns xcs negate time (only when cpuif mode is set * ) t ccn * for details of cpuif mode setting, refer to ?technical manual.? 7. electrical characteristics S1R72C05*** data sheet (rev.1.00) epson 25 7.4.4 ide i/f timing 7.4.4.1 pio read timing code description min. typ. max. units t321 - 0 - ns t322 - 0 - ns t323 80 - - ns t324 - (ap+4) * 16.7 - 3 - ns t325 - (np+4) * 16.7 + 3 - ns t326 50 - - ns t327 10 - - ns t328 0 - - ns t329 - - 25 ns stable stable xhcs0(o) hda[2:0](o) xhior(o) hdd[15:0](i) hiordy(i) t324 t321 t326 t325 t322 t327 t328 t329 t323 data transfer direction: S1R72C05 data xhcs0 hda hda output delay time xhcs0 hda hda hold time xhcs0 xhior xhcs0 setup time xhior xhior xhior assert pulse width xhior xhior xhior negate pulse width xhior xhcs0 xhcs0 hold time hdd xhior data setup time xhior hdd data hold time hiordy xhior xhior output delay time * 1: ap = ide_tmod.assertpulsewidth, np = ide_tmod.negatepulsewidth for detailed information, refer to ?ide transfer mode? in the register description. 7. electrical characteristics 26 epson S1R72C05*** data sheet (rev.1.00) 7.4.4.2 pio write timing code description min. typ. max. units t331 - 0 - ns t332 - 0 - ns t333 80 - - ns t334 - (ap+4) * 16.7 - 3 - ns t335 - (np+4) * 16.7 + 3 - ns t336 50 - - ns t337 0 - 10 ns t338 33 - 45 ns t339 - - 25 ns valid valid xhcs0(o) hda[2:0](o) xhiow(o) hdd[15:0](o) hiordy(i) t334 t333 t336 t335 t332 t337 t338 t339 t331 data transfer direction S1R72C05 data xhcs0 hda hda output delay time xhcs0 hda hda hold time xhcs0 xhiow xhcs0 setup time xhiow xhiow xhiow assert pulse width xhiow xhiow xhiow negate pulse width xhiow xhcs0 xhcs0 hold time xhiow hdd data output delay time xhiow hdd data bus negate time hiordy xhiow xhiow output delay time * 1: ap = ide_tmod.assertpulsewidth, np = ide_tmod.negatepulsewidth for detailed information, refer to ?ide transfer mode? in the register description. 7. electrical characteristics S1R72C05*** data sheet (rev.1.00) epson 27 7.4.4.3 dma read timing stable stable xhcs[1:0](o) hda[2:0](o) hdmarq(i) xhdmack(o) xhior(o) hdd[15:0](i) t343 t341 t345 t346 t347 t348 t342 t349 t34a t344 code description min. typ. max. units t341 70 - - ns t342 50 - - ns t343 17 - - ns t344 0 - - ns t345 0 - - ns t346 - (ap+4) * 16.7 - 3 - ns t347 - (np+4) * 16.7 + 3 - ns t348 30 - 90 ns t349 10 - - ns t34a 0 - - ns data transfer direction: S1R72C05 data xhcs , hda xhdmack a ddress setup time xhior xhcs , had a ddress hold time hdmarq xhdmack xhdmack response time xhior hdmarq negate hdmarq hold time xhdmack xhior xhdmack setup time xhior xhior xhior assert pulse width xhior xhior xhior negate pulse width xhior xhdmack xhdmack hold time hdd xhior data setup time xhior hdd data bus hold time * 1: ap = ide_tmod.assertpulsewidth, np = ide_tmod.negatepulsewidth for detailed information, refer to ?ide transfer mode? in the register description. 7. electrical characteristics 28 epson S1R72C05*** data sheet (rev.1.00) 7.4.4.4 dma write timing valid valid xhcs[1:0](o) hda[2:0](o) hdmarq(i) xhdmack(o) xhiow(o) hdd[15:0](o) t353 t351 t355 t356 t357 t358 t352 t359 t35a t354 code description min. typ. max. units t351 70 - - ns t352 50 - - ns t353 17 - - ns t354 0 - - ns t355 0 - - ns t356 - - ns t357 - - ns t358 30 - 90 ns t359 0 - 10 ns t35a 33 - 45 ns (ap+4) * 16.7 - 3 (np+4) * 16.7 + 3 data transfer direction: S1R72C05 data xhcs , hda xhdmack a ddress setup time xhiow xhcs , hda a ddress hold time hdmarq xhdmack xhdmack response time xhiow hdmarq negate hdmarq hold time xhdmack xhiow xhdmack setup time xhiow xhiow xhiow assert pulse width xhiow xhiow xhiow negate pulse width xhiow xhdmack xhdmack hold time xhiow hdd data output delay time xhiow hdd data bus hold time * 1: ap = ide_tmod.assertpulsewidth, np = ide_tmod.negatepulsewidth for detailed information, refer to ?ide transfer mode? in the register description. 7. electrical characteristics S1R72C05*** data sheet (rev.1.00) epson 29 7.4.4.5 ultra dma read timing xhcs[1:0](o) hda[2:0](o) hdmarq(i) xhdmack(o) xhiow(o) hdd[15:0](i) stable t362 xhior(o) hiordy(i) t361 t364 t365 t363 t363 t368 t366 t366 t367 initiating host pausing (stop) (hdmardy) (dstrobe) code description min. typ. max. units t361 80 - - ns t362 65 - - ns t363 28 - 40 ns t364 4 - - ns t365 4 - - ns t366 15 - - ns t367 30 - - ns t368 - - ide spec. t rfs ns data transfer direction: S1R72C05 data xhcs , hda xhdmack a ddress setup time hdmarq xhdmack xhdmack response time xhdmack xhior(w) envelope time hdd hiordy data setup time hiordy hdd data hold time hiordy hiordy hiordy cycle time hiordy hiordy hiordy cycle time x2 xhior hiordy final strobe time 7. electrical characteristics 30 epson S1R72C05*** data sheet (rev.1.00) ultra dma read timing (continued) xhcs[1:0](o) hda[2:0](o) hdmarq(i) xhdmack(o) xhiow(o) hdd[15:0](o) xhior(o) hiordy(i) t377 t371 t372 t373 t375 t376 t378 t379 crc host terminating device terminating t377 t379 t378 t374 t37a t37b (stop) (xhdmardy) (dstrobe) t374 crc stable code description min. typ. max. units t371 180 - - ns t372 - - ide spec. t rfs ns t373 - - ide spec. t li ns t374 70 - - ns t375 160 - - ns t376 110 - - ns t377 35 - - ns t378 75 - - ns t379 12 - - ns t37a 20 - 38 ns t37b 110 - - ns (crc) data transfer direction: S1R72C05 data stable crc x hior xhiow time to stop assert x hior hiordy final strobe time x hiow hdmarq restricted interlock time hdmarq hdd output delay time hdmarq xhdmack minimum interlock time hiordy xhdmack minimum interlock time x hdmack xhcs0, 1 x hcs0, 1 hold time hdd(crc) xhdmack crc data setup time x hdmack hdd(crc) crc data hold time hdmarq xhior restricted interlock time hiordy xhdmack minimum interlock time 7. electrical characteristics S1R72C05*** data sheet (rev.1.00) epson 31 7.4.4.6 ultra dma write timing xhcs[1:0](o) hda[2:0](o) hdmarq(i) xhdmack(o) xhiow(o) hdd[15:0](o) hiordy(i) xhior(o) valid t381 t384 t385 t386 t387 t388 t389 t38a t389 initiating device pausing t382 t38b (stop) (hstrobe) (xddmardy) code description min. typ. max. units t381 80 - - ns t382 65 - - ns t384 28 - 40 ns t385 ide spec. t li - ide spec. t li ns t386 20 - - ns t387 - (cyc+1) * 16.7 - ns t388 - (cyc+1) * 16.7 - ns t389 - ns t38a - ns t38b 20 - 38 ns - (cyc+2) * 16.7 - t389 * 2 data transfer direction: S1R72C05 data x hcs , hda xhdmack a ddress setup time hdmarq xhdmack x hdmack response time x hdmack xhiow envelope time x hiow hiordy restricted interlock time hiordy xhior unrestricted interlock time hdd xhior data setup time x hior hdd data hold time x hior xhior x hior cycle time x hior xhior x hior cycle time x2 hiordy xhior final strobe time * 1: cyc = ultradmacycle for detailed information, refer to ?ide ultra-dma transfer mode? in the register description. 7. electrical characteristics 32 epson S1R72C05*** data sheet (rev.1.00) 7.4.5 usb i/f timing conforms to usb 2.0 standard 8. connection examples S1R72C05*** data sheet (rev.1.00) epson 33 8. connection examples 8.1 cpu i/f connection example ca[8:1] xbel data[15:0] xcs xrd xwrh/xbeh xwrl/xwr xdreq0 * 1 xdack0 * 2 xdreq1 * 1 xdack1 * 2 xint address[8:1] 16-bit cpu (xwrh/xwrl) connection example data[15:0] xcs xrd xwrh xwrl xdreq0 xdack0 xdreq1 xdack1 xint * 1: open when dma is not used * 2: fixed at inactive level when dma is not used ca[8:1] xbel data[15:0] xcs xrd xwrh/xbeh xwrl/xwr xdreq0 * 1 xdack0 * 2 xdreq1 * 1 xdack1 * 2 xint address[8:1] 16-bit cpu (xbeh/xbel) connection example data[15:0] xcs xrd xbeh xwr xdreq0 xdack0 xdreq1 xdack1 xint xbel * 1: open when dma is not used * 2: fixed at inactive level when dma is not used 8. connection examples 34 epson S1R72C05*** data sheet (rev.1.00) 8.2 usb i/f connection example 8.2.1 for qfp15-128 (device periphery) 128 1 xi xo 2 3 4 5 6 8 vss vss hvdd dm_b dp_b to usb b_connector lvdd(1.8v 0.15v) vss hvdd(3.3v 0.3v) vbus_b 6.2k 1% 1u 0.1u 0.1u S1R72C05 qfp15-128 cg, cd, rd: as required the oscillator circuit must match the quartz resonator. contact the quartz resonator manufacturer for detailed information on circuit constants. 10 9 10 11 12 13 vss r1_b vss 7 vss lvdd hvdd top view rd cg cd 1u 127 lvdd 1u lvdd vss 14 15 1u for detailed information on usb peripheral circuits, refer to the "pcb design guidelines for s1r72v series usb 2.0 high-speed devices." static protection varistor select power supply elements carefully; their pe rformance will affect usb signal waveform quality. 8. connection examples S1R72C05*** data sheet (rev.1.00) epson 35 8.2.2 for qfp15-128 (host periphery) vss hvdd vss dp_a lvdd(1.8v 0.15v) vss hvdd(3.3v 0.3v) S1R72C05 qfp15-128 117 116 115 114 112 hvdd dm_a 113 top view r1_a 111 vss 110 109 lvdd vbusen_a 108 107 vbusflg_a to usb a_connector vcc(5.0v 0.5v) lvdd 119 118 vss 6.2k 1% 0.1u 1u 0.1u 1u for detailed information on usb peripheral circuits, refer to the "pcb design guidelines for s1r72v series usb 2.0 high-speed devices." the vbus circuit is shown for reference purposes only and should not be interpreted as a recommended configuration. select components and circuit type to suit individual system requirements. caution is required with components using fet switches, since a current flows from the out terminal to the in terminal if the out terminal voltage exceeds the in terminal voltage, whether enabled or disabled by the parasitic diode between the source and drain. vbus control circuit static protection varistor flg enb out select power supply elements carefully; their pe rformance will affect usb signal waveform quality. 8. connection examples 36 epson S1R72C05*** data sheet (rev.1.00) 8.2.3 for pfbga8ux121/pfbga10ux121 (device periphery) xo lv dd r1_ b hv dd xi vs s vs s vs s cd rd cg 6.2k 1% to usb b_connector c11, c12, rd: as required the oscillator circuit must match the quartz resonator. contact the quartz resonator manufacturer for detailed information on circuit constants. lvdd(1.8v 0.15v) vss hvdd(3.3v 0.3v) a2 b1 b2 c1 c2 d1 d2 e1 1u 10 S1R72C05 pfbga8ux121 pfbga10ux121 top view dm _b f1 dp _b g1 vs s f2 hv dd g2 vbu s_b g3 lv dd a3 1u lv dd h1 vs s h2 for detailed information on usb peripheral circuits, refer to the "pcb design guidelines for s1r72v series usb 2.0 high-speed devices." 1u 0.1u 0.1u 1u static protection varistor select power supply elements carefully; their pe rformance will affect usb signal waveform quality. 8. connection examples S1R72C05*** data sheet (rev.1.00) epson 37 8.2.4 for pfbga8ux121/pfbga10ux121 (host periphery) dp _a dm _a hv dd hv dd vs s vbu sen _a r1_ a vs s vbu sfl g_a lvdd(1.8v 0.15v) vss hvdd(3.3v 0.3v) 0.1u a5 a6 a7 a8 b5 b6 b7 b8 c6 S1R72C05 pfbga8ux121 pfbga10ux121 top view lv dd vs s b9 a9 to usb a_connector 6.2k 1% vcc(5.0v 0.5v) lv dd a4 vs s b4 for detailed information on usb peripheral circuits, refer to the "pcb design guidelines for s1r72v series usb 2.0 high-speed devices." the vbus circuit is shown for reference purposes only, and should not be interpreted as a recommended configuration. select the components and circuit type to suit individual system requirements. caution is required with components using fet switches, since a current flows from the out terminal to the in terminal if the out terminal voltage exceeds the in terminal voltage, whether enabled or disabled by the parasitic diode between the source and drain. 1u 0.1u 1u static protection varistor flg enb out select power supply elements carefully; their pe rformance will affect usb signal waveform quality. 9. product codes 38 epson S1R72C05*** data sheet (rev.1.00) 9. product codes table 9.1 product codes product code product type S1R72C05b08 **** pfbga8ux121 package S1R72C05b10 **** pfbga10ux121 package S1R72C05f15 **** qfp15-128 package 10. external dimension diagrams S1R72C05*** data sheet (rev.1.00) epson 39 10. external dimension diagrams refer the attached diagrams on the end of this document. qfp package(qfp15-128) bga package (pfbga8ux121) bga package (pfbga10ux121) external dimension diagrams 40 epson S1R72C05*** data sheet (rev.1.00) revision history description of revision date rev. page (old issue) classification description 08/21/2007 1.00 all pages new new issue 2900-0002-01(rev.1.1) p-tfbga-121-0808-0.65(pfbga8u-121) a1 corner 1 a c d e f g b bottom view index a1 corner top view z z d e a e b x y 1 0.22 0.75 0.65 0.08 d e symbol a min nom max d e a a 1 e z d ? e 2 3 4 5 6 7 8 9 10 k j h 0.27 0.37 z e 0.75 11 l - - - - - - - - - - - - - - - - - - - 8 8 1.2 0.1 - - - a1 corner 3 2 1 4 8 7 6 5 11 10 9 h a c d e f g b j k l bottom view index a1 corner top view z z d e a e b x y 1 0.3 1 1 0.38 0.8 0.48 0.08 0.1 d e symbol a min 10 10 nom max 1.2 d e a a 1 e z d ? e z e 2900-0002-01(rev.1.1) - - - - - - - - - - - - - - - - - - - p-tfbga-121-1010-0.80(pfbga10u-121) international sales operations america epson electronics america, inc. headquarters 2580 orchard parkway san jose , ca 95131,usa phone: +1-800-228-3964 fax: +1-408-922-0238 sales offices northeast 301 edgewater place, suite 210 wakefield, ma 01880, u.s.a. phone: +1-800-922-7667 fax: +1-781-246-5443 europe epson europe electronics gmbh headquarters riesstrasse 15 80992 munich, germany phone: +49-89-14005-0 fax: +49-89-14005-110 asia epson (china) co., ltd. 23f, beijing silver tower 2# north rd dongsanhuan chaoyang district, beijing, china phone: +86-10-6410-6655 fax: +86-10-6410-7320 shanghai branch 7f, high-tech bldg., 900, yishan road, shanghai 200233, china phone: +86-21-5423-5522 fax: +86-21-5423-5512 epson hong kong ltd. 20/f., harbour centre, 25 harbour road wanchai, hong kong phone: +852-2585-4600 fax: +852-2827-4346 telex: 65542 epsco hx epson electronic technology development (shenzhen) ltd. 12/f, dawning mansion, keji south 12th road, hi- tech park, shenzhen phone: +86-755-2699-3828 fax: +86-755-2699-3838 epson taiwan technology & trading ltd. 14f, no. 7, song ren road, taipei 110 phone: +886-2-8786-6688 fax: +886-2-8786-6660 epson singapore pte., ltd. 1 harbourfront place, #03-02 harbourfront tower one, singapore 098633 phone: +65-6586-5500 fax: +65-6271-3182 seiko epson corporation korea office 50f, kli 63 bldg., 60 yoido-dong youngdeungpo-ku, seoul, 150-763, korea phone: +82-2-784-6027 fax: +82-2-767-3677 gumi office 2f, grand b/d, 457-4 songjeong-dong, gumi-city, korea phone: +82-54-454-6027 fax: +82-54-454-6093 seiko epson corporation semiconductor operations division ic sales dept. ic international sales group 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 document code: 411234700 first issue september 2007 printed in japan h |
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